Download Analog Circuit Design: High-Speed Analog-to-Digital by M. Steyaert, K. Uyttenhove (auth.), Rudy J. van de Plassche, PDF

By M. Steyaert, K. Uyttenhove (auth.), Rudy J. van de Plassche, Johan H. Huijsing, Willy Sansen (eds.)

This publication includes the prolonged and revised variants of all of the talks of the 9th AACD Workshop held in inn Bachmair, April eleven - thirteen 2000 in Rottach-Egem, Germany. The neighborhood association was once controlled by way of Rudolf Koch of Infineon applied sciences AG, Munich, Germany. this system consisted of six tutorials according to day in the course of 3 days. specialists within the box awarded those tutorials and cutting-edge details is communicated. The viewers on the finish of the workshop selects software themes for the next workshop. this system committee, including Johan Huijsing of Delft college of know-how, Willy Sansen of Katholieke Universiteit Leuven and Rudy van de Plassche of Broadcom Netherlands BV Bunnik elaborates the chosen subject matters right into a three-day software and selects specialists within the box for presentation. every one AACD Workshop has given upward thrust to booklet of a booklet by way of Kluwer entitled "Analog Circuit Design". a sequence of 9 books in a row presents necessary info and strong overviews of all analog circuit ideas relating layout, CAD, simulation and gadget modeling. those books should be noticeable as a connection with these humans fascinated by analog and combined sign layout. the purpose of the workshop is to brainstorm on new and useful layout principles within the quarter of analog circuit layout. it's the desire of this system committee that this 9th e-book maintains the culture of rising contributions to the layout of analog and combined sign platforms in Europe and the remainder of the world.

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Extra info for Analog Circuit Design: High-Speed Analog-to-Digital Converters; Mixed Signal Design; PLL’s and Synthesizers

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When the noise (rms) exceeds quarter LSB, the error waveform becomes almost random and the spurs virtually disappear. B. 44/(2n/3) FS, have uncorrelated offsets on the order of a quarter LSB, the periodicity of this sawtooth portion significantly diminishes, and so does the corresponding peak harmonic at 2"11: fin. With this peak removed, SFDR is limited by the low-order -9n dB harmonics, 6-dB improvement on SFDR is possible. It is interesting to notice that the effect of random offsets on the lower-order harmonics is opposite to that on the high-order peak.

If the output common mode goes up, this pulls the common mode of the gates of Ml and M2 up, which causes more current to flow, which tends to bring the output common mode down. The preamp is reset during one half of every clock cycle by turning on the reset switch. As soon as the reset goes low, the amplifier simply 'integrates' the input and the output grows in a linear fashion. This is in contrast to amplifying type preamps that have been used in other high speed A/D converters [1]. The integrating type preamp used above requires a smaller ampunt of power to achieve a desired dynamic gain.

As a result, calibration [23], [24], [25], [26], [27], trimming, and error averaging [28], are necessary for resolution of 12b and above. 5b/stage architecture still can not comfortably meet the SFDR specification of over 80 dB (Table 1). Gain accuracy over the nominal value is necessary for the required SFDR. B. multibitlstage This research investigates the fundamental limitations to SFDR with pure analog solution. 5b/stage has to be removed by increasing the first stage resolution [29]. Issues arise from the multibit/stage implementation.

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